ece552
spring 2026 · projects
PROJECTS
Project 1: RISC-V Assembly Language Project 2: Digital Design and Debugging Project 3: Single-Cycle Processor Project 4: Basic Pipelined Processor Project 5: Forwarding and Branch Prediction Project 6: Multi-Cycle Memory Project 7: Cache Integration Project 8: Extra Credit
REFERENCE
Verilog Rules Reference Materials
ece 552 / projects › Project 8: Extra Credit
Home

Project 8: Extra Credit

UW–Madison ECE 552: Introduction to Computer Architecture · Spring 2026

Project Introduction

In this project phase, you have an opportunity to earn extra credit. You can earn a maximum of 5% improvement to your final course grade through these activities.

Instructions

We have an autograder on Gradescope (still pending, will announce when it is fixed) which will run the Coremark benchmark on your processor. If you a) pass all correctness tests from Project 7, b) achieve correctness on the benchmark, and c) beat the reference implementation's CPI by at least 10%, you will receive a 1% boost to your final course grade.

The top 3 teams in the class in terms of CPI will receive an additional 1% boost to the final course grade.

You may also receive extra credit for completing specific optimizations. These optimizations must be accompanied by a short report detailing your design and indicating CPI of your processor before and after implementation. Each optimization will be worth 1%.

  1. Prefetcher
  2. Increase cache associativity
  3. Improved branch predictor

Any other optimization may be possible, but must be approved in writing. Please send an email to both TAs describing what you would like to implement.

You must complete a short report to receive extra credit.

# On this page
Project Introduction Instructions Submission Instructions
ECE 552 © 2026 Course Staff UW–Madison
Introduction to Computer Architecture