Project 6: Multi-Cycle Memory

UW–Madison ECE 552: Introduction to Computer Architecture · Spring 2026

Project Introduction

In this project phase, you will adapt your processor from Project 5 to be able to handle a memory that has more than one cycle of latency. You will also create a schematic for a cache that you will implement in Project 7.

Implementations must be created using Verilog; SystemVerilog will not be allowed and will result in a grade of 0 for Problem 1 if used. This assignment is designed to be completed in a group of 2-3. Collaboration between groups is not permitted. IMPORTANT: Make your final submissions in your groups on Gradescope. If you do not, the teaching staff will have to do this manually.

You may not use generative artificial intelligence (e.g. ChatGPT). For this assignment, LLMs will not be helpful and overly relying on them may make this project phase and subsequent phases significantly harder to complete.

This project will be worth 2.5% of your final course grade. The automated tests on Gradescope cover most of the points for the project, but the schematic is worth a fair portion.

All material is available in the Project 6 and 7 repository on Gitlab. You can clone the repository locally or on a CSL machine.

If there are any issues with Gradescope or the files provided, please post on Piazza rather than emailing. If you are having difficulty with this project, the TAs are holding office hours several times a week (check Canvas) where you can receive assistance.

Good luck!

Problem 1: Multi-Cycle Memory Implementation

We have updated the testbench from the previous projects to use a multi-cycle memory rather than one with zero-cycle latency. You can find this testbench in the Project 6 and 7 repository on Gitlab.

We also updated the hart interface, which you can find in the repository. There is also a file called tb_memory.v which is the stalling memory module we are using. You should not submit tb_memory.v to Gradescope.

Note that both the instruction and data memories will now stall before servicing requests. Note also that your optimizations from Project 5 effectively become useless due to this. In Project 7, you will add a cache which will enable zero-cycle latency for cached addresses and make your optimizations effective again.

Problem 2: Cache Schematic

Create a schematic for the finite state machine for a two way set-associative cache. The cache should follow the write-through and write-allocate policies.

You will create this cache module in Project 7. Project 7 is not yet available as of writing this spec, so expect more files to become available in the repository once it is posted.

Submission Instructions

Submit the following files to the appropriate Gradescope assignment:

Filenames must match exactly. Please double check to ensure that you have submitted all of the required files.

This project will be worth 2.5% of your final course grade.