Project 7: Cache Integration

UW–Madison ECE 552: Introduction to Computer Architecture · Spring 2026

Project Introduction

In this project phase, you will design and implement a two way set-associative cache which will reduce the overall CPI of your processor. This is the last required project for ECE 552.

Implementations must be created using Verilog; SystemVerilog will not be allowed and will result in a grade of 0 for Problems 1 and 2 if used. This assignment is designed to be completed in a group of 2-3. Collaboration between groups is not permitted. IMPORTANT: Make your final submissions in your groups on Gradescope. If you do not, the teaching staff will have to do this manually.

You may not use generative artificial intelligence (e.g. ChatGPT). For this assignment, LLMs will not be helpful and overly relying on them may make this project phase and subsequent phases significantly harder to complete.

This project will be worth 5% of your final course grade. The automated tests on Gradescope comprise the majority of the points (mostly performance for this project). The schematic is worth a fair portion.

All material is available in the Project 6 and 7 repository on Gitlab. You can clone the repository locally or on a CSL machine.

If there are any issues with Gradescope or the files provided, please post on Piazza rather than emailing. If you are having difficulty with this project, the TAs are holding office hours several times a week (check Canvas) where you can receive assistance.

Good luck!

Problem 1: Cache Implementation

Implement the cache from the schematic that you designed in Project 6. The starter file, cache.v, is available in rtl folder in the Project 6 and 7 repository on Gitlab. You can submit this file alone to Gradescope to determine whether or not your cache is functional.

The cache testbench and memory file are also available in the repository in the tb folder.

The cache should follow the write-through and write-allocate policies.

Problem 2: Cache Integration

Integrate your cache into your processor implementation. You can do this by hooking the cache signals up to the memory interface signals in your processor. You can implement the caches in any order, but it is recommened to first add in the instruction cache, then the data cache.

Your code should pass correctness tests on Gradescope before the caches are added, after one of them is added, and after both are added. Your code should pass performance tests once both caches are added.

Submission Instructions

Submit the following files to the appropriate Gradescope assignment:

Filenames must match exactly. Please double check to ensure that you have submitted all of the required files.

This project will be worth 5% of your final course grade. The results of any manually graded content will be made available after the deadline.