Project 5: Forwarding and Branch Prediction

UW–Madison ECE 552: Introduction to Computer Architecture · Spring 2026

Project Introduction

In this project phase, you will add optimizations to the processor that you pipelined in Project 4. It is recommended to start this project early.

Implementations must be created using Verilog; SystemVerilog will not be allowed and will result in a grade of 0 for Problem 2 if used. This assignment is designed to be completed in a group of 2-3. Collaboration between groups is not permitted. IMPORTANT: Make your final submissions in your groups on Gradescope. If you do not, the teaching staff will have to do this manually.

You may not use generative artificial intelligence (e.g. ChatGPT). For this assignment, LLMs will not be helpful and overly relying on them may make this project phase and subsequent phases significantly harder to complete.

This project will be worth 5% of your final course grade. The automated tests on Gradescope comprise the majority of the points (mostly performance for this project). The schematic is worth a fair portion.

All material is available in the Project 4 and 5 repository on Gitlab. You can clone the repository locally or on a CSL machine.

If there are any issues with Gradescope or the files provided, please post on Piazza rather than emailing. If you are having difficulty with this project, the TAs are holding office hours several times a week (check Canvas) where you can receive assistance.

Good luck!

Problem 1: Schematic

Update your schematic from Project 4 to include the optimization elements (EX-EX forwarding, MEM-EX forwarding, predict not taken branches).

Since labelling the bit width of every signal (with a width of greater than 1) for every pipeline stage is tedious, you may label the bit width in the first stage in which the signal appears and represent the width of that signal (if greater than 1) with just a slash in subsequent stages.

Problem 2: Optimizations

You must add the following optimizations to the processor that you pipelined in Project 4:

1. EX-EX forwarding
2. MEM-EX forwarding
3. Branches are predicted to not be taken

You are allowed to implement additional optimizations if you would like, but these are the minimum optimizations required to receive full credit for this project. Your processor will be graded both on accuracy and on performance in this project, and will be run against a reference model in Gradescope to do so.

Again, all material is available in the Project 4 and 5 repository on Gitlab.

Resources

The RISCV-32I specification document is the primary document to reference how instructions are implemented.

The reference sheet is helpful when writing programs or as a quick reference.

You may find this simulator helpful for visualizing how your processor should execute, and for verifying functional correctness and performance.

We also recommend using this decoder to assemble RISC-V instructions to test and examine instructions when debugging.

Gradescope

Submit your code to Gradescope as often as you would like to verify your processor. Please note that we are enforcing Verilog coding rules for this project. You can find a centralized list of these rules here. The rule-checking script will run every time you submit your processor. The rule checking script will first check for compiler errors, then disallowed constructs. Once your code is passing the rules check, we will perform a trace comparison between your processor and our reference implementation.

Submission Instructions

Submit the following files to the appropriate Gradescope assignment:

Filenames must match exactly. Please double check to ensure that you have submitted all of the required files.

This project will be worth 5% of your final course grade. The results of any manually graded content will be made available after the deadline.