ECE552 Fall 2026
Project 1: RISC-V Assembly Language Project 2: Digital Design and Debugging Project 3: Single-Cycle Processor Project 3: Extra Credit - FPGA Demo Project 4: Basic Pipelined Processor Project 5: Forwarding and Branch Prediction Project Schedule Verilog Rules Reference Materials
ECE 552 / Reference Materials
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Reference Materials

UW-Madison ECE 552: Fall 2026

Downloads

RISC-V32I Instruction Set Reference Sheet v1.1

RISC-V32I Specification v1.0

Verilog Rules

Helpful Online Resources

Computer Organization and Design MIPS Edition (552 Textbook)

Ripes RISC-V Visualizer

RISC-V Instruction Encoder/Decoder

2026 ECE 552 Course Staff, University of Wisconsin-Madison