ece552
spring 2026 · projects
PROJECTS
Project 1: RISC-V Assembly Language Project 2: Digital Design and Debugging Project 3: Single-Cycle Processor Project 4: Basic Pipelined Processor Project 5: Forwarding and Branch Prediction Project 6: Multi-Cycle Memory Project 7: Cache Integration Project 8: Extra Credit
REFERENCE
Verilog Rules Reference Materials
ece 552 / home
Verilog Rules Reference
COURSE · UW–Madison · Spring 2026

ECE 552: Introduction to Computer Architecture

Course materials for the Spring 2026 offering of ECE 552. Browse projects below, or jump to the Verilog rules and reference materials.

Heads up Drafted projects are visible but locked until release. All assignments are mirrored to the course GitLab.
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Projects

Project 1: RISC-V Assembly Language /project1/ Project → Project 2: Digital Design and Debugging /project2/ Project → Project 3: Single-Cycle Processor /project3/ Project → Project 4: Basic Pipelined Processor /project4/ Project → Project 5: Forwarding and Branch Prediction /project5/ Project → Project 6: Multi-Cycle Memory /project6/ Project → Project 7: Cache Integration /project7/ Project → Project 8: Extra Credit /project8/ Project →
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Reference

Verilog Rules /rules/ Reference → Reference Materials /html/reference Reference →
ECE 552 © 2026 Course Staff UW–Madison
Introduction to Computer Architecture